791 views
3 votes
3 votes

Cache can hold 512KB. Data is transferred between main memory and Cache Block of 32B each. Main memory consists of 4GB. If cache memory is 2-way set associative then the hexadecimal main memory address (ABABABAB)is mapped to which cache set?

Answer give by them is Line offset= 2B5B and Set offset= 1D5D.

I understood how they got set offset value but didn't understand how they got the answer for line offset.

Please help.

1 Answer

Best answer
6 votes
6 votes

See first of all we have to see the CPU generated address format based on the constraints given

No of lines = Cache size  / cache blocksize 

                =  512 K B /  32 B

                =  214

No of sets hence  = 213

Hence no of set bits  =  13 bits

Block offset  = log2 (32)   =  5 bits

So no of tag bits  =  32 - 13 - 5  =  14 bits

Given memory address : A B A B A B A B  

                   = 1010 1011 1010 1011 1010 1011 1010 1011

So set bits (middle 13 bits after 14 tag bits)  =  11 1010 1011 101 which can be rewritten as 

                                                                 =  0001 1101 0101 1101

                                                                 =  1 D 5 D

Hence set offset   =  1 D 5 D

There is no line offset concept in set associative cache as given a set , a line can be mapped to any of the ways..

selected by

Related questions

0 votes
0 votes
1 answer
2
tishhaagrawal asked Dec 5, 2023
335 views
Can anybody explain why are they dividing the number of pages by page size?According to me, it should be – Page table size = Number of entries * entry sizei.e PT size =...