See first of all we have to see the CPU generated address format based on the constraints given
No of lines = Cache size / cache blocksize
= 512 K B / 32 B
= 214
No of sets hence = 213
Hence no of set bits = 13 bits
Block offset = log2 (32) = 5 bits
So no of tag bits = 32 - 13 - 5 = 14 bits
Given memory address : A B A B A B A B
= 1010 1011 1010 1011 1010 1011 1010 1011
So set bits (middle 13 bits after 14 tag bits) = 11 1010 1011 101 which can be rewritten as
= 0001 1101 0101 1101
= 1 D 5 D
Hence set offset = 1 D 5 D
There is no line offset concept in set associative cache as given a set , a line can be mapped to any of the ways..