retagged by
1,744 views
7 votes
7 votes
A non-pipeline processor has a clock rate 3 GHz and an average CPI of 4. An upgrade to the processor introduce 5 stage pipeline. How ever due to internal delay the clock rate of the new processor has to be reduces to 2 GHz. What is the speed-up of pipeline over non-pipeline?
retagged by

2 Answers

4 votes
4 votes

Speedup = TWP/TP.

Twp = Time taken without pipelining.

TP = Time taken with pipelining.

Let number of instructions = n

TWP = n * 4 * (1/3)ns     [freq = 3GHz, so clock = (1/3)ns] [AVG CPI = 4]

T= [(1 * 5) + (n-1)*1] * (1/2)ns     [freq = 2GHz, so clock = (1/2)ns] [AVG CPI = 1]

Speedup = $\frac{n*4*(1/3)}{[(1*5)+(n-1)*1]*(1/2)}$ = $\frac{8n}{3n+12}$

For large number of instructions, Speedup = $\lim_{n \to ∞} \frac{8n}{3n+12}$ = 2.67

edited by
2 votes
2 votes

speed up =cpinonpipe* cycle time  / cpipipe*cycle time=4*2/1*3 =2.67
assumption for large no of instruction
speed up=Limn->∞  ( n*4*cycle timenonpipi  /(k+n-1)*cycle timepipe)
                  =4*cycle timenonpipi  /cycle timepipe

Related questions

0 votes
0 votes
1 answer
1