Consider a system in which bus cycle takes 500 ns. Transfer of bus control in either direction, from processor to device or vice-versa, takes 250 ns.One of the IO device has data transfer rate of 75 KB/sec and employs DMA. Data are transfer red one byte at a time.
(a) Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus mastership prior to the start of block transfer and maintains control of the bus until the whole block is transferred. For how long would the device tie up with the bus when transferring a block of 256 bytes?
b) calculate the same for cycle stealing mode
Please explain in which mode we use bus cycle time and why?