Generally questions like this cannot be answered without the data path diagram. Assuming external memory bus is not connected to interal register to ALU Bus, yes you are correct I2 and I3 can be executed parellely. But as you are suggesting I2,I3 and I4 cannot be executed in the same clock cycle as the instruction will be not available in MBR until I2 completes. This will be timeline for the above set of instructions.
T1 : I1
T2 : I2 and I3
T3 : I4