It is given that on an average an instruction requires 6 cycles and the CPU is busy 95% of the time in executing those instructions. Out of these 6 cycles, 3 cycles are needed for memory operations. During this time DMA cannot access the memory.
So only 3 cycles are left for DMA to use for 95% of the time. For 95% time DMA uses
0.95∗3 cycles
For rest 5% time, CPU isn't executing instructions, so all cycles are available, so DMA uses 0.05∗6 cycles
Total cycles available for DMA = (0.05∗6+0.95∗3) cycles
In 1second, CPU can execute 10^6 instructions. So rate of transfer = 10^6∗(0.05∗6+0.95∗3)=3.15∗106