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Consider a memory system consists of a single external cache with an access time of 20ns and a hit rate of 0.92, and a main memory with an access time of 60ns. Now we add virtual memory to the system. The TLB is implemented internal to the processor chip and takes 2ns to do a translation on a TLB hit. The TLB hit ratio is 98%, the segment table hit ratio is 100% and the page table hit ratio is 50%. What is the effective memory access time of the system with virtual memory?

  1.   27.3ns
  2.   28.2ns
  3.   29ns
  4.   29.44ns

1 Answer

7 votes
7 votes
Time to access TLB = 2 ns. Main memory access time = 60ns. External cache access time = 20 ns.

$t_{eff}=t_{TLB}+(1-hit_{TLB})\;(t_{seg}+t_{page})+ t_{cache}+(1-hit_{cache})\;t_{RAM}$

$=2+0.02(20+20+0.5*60) + 20 + 0.08*60 = 28.2$ ns.

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