Operand forwarding in pipeline

Question

A $5$ stage pipelined processor has the following stages:

• $IF$ : instruction fetch
• $ID$ : instruction decode
• $EX$ : execute
• $MA$ : memory access
• $WB$ : write back

$$\large\color{red}{IF \rightarrow ID\rightarrow EX\rightarrow MA\rightarrow WB}$$

• Each stage needs one cycle for all instructions.

$\begin{matrix} I_1.&\text{Load} &R_1 ,\;[1000] &&& : \quad &R_1&\leftarrow &M[1000] \\ I_2.&\text{Load} &R_3 \; ,\; 5(R_2) &&& : \quad &R_3&\leftarrow &M[R_2+5] \\ I_3.&\text{MUL} &R_4 \; ,R_1\;,R_3 \; &&& : \quad &R_4&\leftarrow &R_1\;*\;R_3 \\ I_4.&\text{DIV} &R_5 \; ,R_1\;,R_4 \; &&& : \quad &R_5&\leftarrow &R_1\; \div \;R_4 \\ I_5.&\text{SUB} &R_6 \; ,R_4\;,R_5 \; &&& : \quad &R_6&\leftarrow &R_4\;-\;R_5 \\ \end{matrix}$

No. of cycles needed to execute these instructions using operand forwarding?

Comments

Why 2 ID for I3? Why not stall?

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@Debashish deka here by default : operand forwarding is used only from

1.MA OUTPUT REGISTER TO INPUT REGISTER OF EX

2.EX OUTPUT REGISTER TO EX INPUT REGISTER

3.SPLIT PHASE IS ONLY DURING THE WB TO RD PHASE NO WHERE ELSE WE SHOULD ASSUME SPLIT PHASE (BY DEFAUlT WE CAN CONSIDER )

IN GATE 2015 WHAT THEY MEANT BY OPERAND FORWARDING BETWEEN EX TO RD PHASE MEANS THE ABOVE MENTIONED 2ND CASE

CORRECT ME IF I AM WRONG

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For operand forwarding clarity in depth, I recommend following videos

https://youtu.be/Bm6ydj9-0O4

https://youtu.be/IOdtauyIIl0

 

Answer 1

Operand Forwarding 

• Data is forwarded when it is ready . It  depends on the type of instruction . for $I_1$ and $I_2$ data can be forwarded from MA stage for other instruction data can be forwardd from EX stage
• The previous clock cycle  must complete before data being forwarded . Unless split phase technique is used
• Use split phase access if data is ready- like between WB/RD
• and also when operand forwarding happens from EX-ID stages, but not from EX-EX stages. We cannot do split phase access between EX-EX, because there is no guarantee that the instruction execution can be done within a half phase.[mostly when it is given in question that there is operand forwarding from A stage to B stage eg:https://gateoverflow.in/8218/gate2015-2_44 ]
• Here nothing has mentioned about data forwarding from particular stage to other so we can chose the best option possible.

Using Operand Forwarding Techinique it will take 10 clock cycles

Reference

• https://gateoverflow.in/1391/gate2005-68
• https://gateoverflow.in/8218/gate2015-2_44

Comments

Forwrding generally happens in EX to EX or MA to EX

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Why can’t instruction I5 do Instruction Fetching at t5?

Though the answer is coming out to same, why IF can’t be executed at t5 instead of at t6 for instruction I5?

REASON: We cannot push another instruction in the pipeline when some other instruction is stalled at IF stage. As I4 was stalled at t = 5, that’s why we can’t IF for I5 at t = 5. At t= 6, I4 is freed from the stall, hence for I5, we started the IF stage at t =6. So, unless the next stage starts IF stage of the next instruction cannot start (otherwise buffer might get corrupted).

Also, @pC Sir in your answer, you have used operand forwarding and split phasing both, right?

Why I am saying that you have used split phasing is because I3 depends on I1 for register R1, and at t=4 , for instruction I1 we have MA stage and also at t = 4, for instruction I2 we have ID stage, which means both the stages are working in parallel. I3 requires R1 which is loaded into memory in I1 at t = 4, so at the falling edge of the clock cycle of t = 4, the correct value of R1 is available at the MA stage of instruction I1 which is split phased with ID stage of  I3. Thus, I3 receives the correct value of R1. Am I right?

I drew the table and found that if I only use operand forwarding and no split phasing, then it takes 13 cycles. I1 ends at t5, I2 ends at t6, I3 ends at t9, I4 ends at t11, I5 ends at t13.

Please help @adad20

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How it is possible to forward operand from MA stage of I3 to EX of I5 , I3 don't even use this stage as there is no load/store instruction