Consider a pipelined system with 4 phases
- FI - Fetch Instruction
- Decode and Calculate Address
- Fetch Operand
- Execute Instruction
Each phase require 1 clock cycles .
Instructions
- Load R1 <-m[312]
- Add R2 <- R1+ m[313]
- INC R3<-R2+1
- Store M[314] <- R3
What is the number of Clock cycles required (assume no measures are taken to avoid any type of pipeline hazards )
What is the anser here IF pipeline Forwarding Technique is also used ?