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Consider a pipelined system with 4 phases

  1. FI - Fetch Instruction
  2. Decode and Calculate Address
  3. Fetch Operand
  4. Execute Instruction

Each phase require 1 clock cycles . 

Instructions

  1. Load R1 <-m[312]
  2. Add  R2 <- R1+ m[313]
  3. INC  R3<-R2+1
  4. Store M[314] <- R3

What is the number of Clock cycles required (assume no measures are taken to avoid any type of pipeline hazards )

What is the anser here IF pipeline Forwarding Technique is also used ?  

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This is Instruction/Cycle diagram.

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