0 votes 0 votes I1: L R0, loc 1; R0 <= M[loc1] I2: A R0, R0; R0 <= R0 +R0 WB of I1 and ID stage of I2....should be overlapping or not? How to consider this case...as in gate previous questions answers are changing according to the given options? CO and Architecture pipelining co-and-architecture + – vaishali jhalani asked Jan 10, 2017 • retagged Nov 13, 2017 by Arjun vaishali jhalani 256 views answer comment Share Follow See 1 comment See all 1 1 comment reply Amit.kumar commented Jun 5, 2017 reply Follow Share i think answer wont change even either ID of i2 overlaps with EX stage or WB stage of i1. 0 votes 0 votes Please log in or register to add a comment.