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Which instruction is branch condition? The question is not clear.

+1 vote

in this question  instruction is :  I1-->I2--->I3-->I4-->I5-->I6-->I12-->I13-->I14--->I15--->I16

and its 5 stage pipeline so K=5 and n=  11

here branch penality =  target address available - 1

execution time of pipeline =  (K+n-1)* tP + (branch penality)* tp

=  (5+11-1)*10 +(3-1)*10

=  15*10 + 2*10

=  170 ns

option A is correct

selected

another way to look into this problem w/o formula is

1st instn. is going to take 50ns and after that till I6 every instn will take 10ns so till completion of 100ns.

now when I5 is in its mem. stage , I6 is in its execute stage and after execution stage as ques. describes we have address of the next inst.

so I12 can proceed with the 4th clock cycle of I6 so (here 2 cycles wasted and 2 cycles can be overlapped by I12  which will make I12  to take 30 more ns to execute itself. now after that each inst. can be done in 10ns (from I13 to I16 ) which will be 4*10 = 40

so in total 50 + 5*10( because I6) will also be executed next. + 30(due to overlapping after execute inst.) + 4*10 =  170ns.

correct me if am wrong!

It should be like this, right?

exactly @sushant