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Consider a Hypothetical system in which program execution gives 100 stall cycles per instruction on an average. There are 240 and 130 misses in L1 (Level-1) and L2 (Level-2) caches out of total 1000 CPU references. If L2 to memory miss penalty is twice the L2 hit time, what are “hit time of L2” and “L2 to memory miss penalty” values respectively (in cycles)?
[Given 2.5 memory references per instructions].
 

  • (A)100, 200
  • (B)200, 400
  • (C)300, 600
  • (D)400, 800

Ans given op(D).......i got 80,160

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Average stalls per instruction = $\frac{Memory\ Access}{Instruction} \times \frac{Miss}{Memory\ Access} \times\frac{Cycles}{Miss}$

Let, hit time of L2 = x

avg stalls per instruction = stalls due to L1 miss + stalls due to L2 miss
$100=2.5 \times \frac{240}{1000} \times x + 2.5 \times \frac{130}{1000} \times 2x\\ 100 =0.6x+065x\\ 100 =1.25x\\ x=\frac{100}{1.25}\\ x=80$

$\therefore$ Hit time of L2 cache = 80 cycles
and L2 to memory miss penalty = 160 cycles

ref: http://cs.uwec.edu/~buipj/teaching/cs.352.f12/lectures/lecture_08.html

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