0 votes 0 votes my question is even in case of a miss the cache will still be accessed and then main memory, right? please explain this when to consider higher memory level access time and when not to consider it CO and Architecture co-and-architecture cache-memory virtual-gate-test-series + – Pankaj Joshi asked Jan 13, 2017 • edited Apr 14, 2019 by Lakshman Bhaiya Pankaj Joshi 311 views answer comment Share Follow See 1 comment See all 1 1 comment reply santhoshdevulapally commented Jan 17, 2017 reply Follow Share if the question not containg hierarchy word then only use simultaneous otherwise use hierarchial. It is hierarchial organization so if there is any miss we have to transfer to lower levels and then access it. So answer is 42 only. 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes if nothing is mentioned, it is following simultaneous access in memory hirarchy . Avg access time = cache hit * cache access time + missRate * hit rate in 2nd level * 2nd level access time = .98 * 12 + .02 * 1 * 1500 = 41.76 ns pps121 answered Jan 26, 2017 pps121 comment Share Follow See all 0 reply Please log in or register to add a comment.