Virtual Gate Test Series: CO & Architecture - Data Path Delay

Question

A multiplier data path is shown below

In the avove data path the delay of the elements are as follows$:$

$R_{1}$ and $R_{2}:2ns$

$\text{ADDER:30ns}$

$R_{3}$ and $R_{4}:10ns$

$\text{MUX:25ns}$

The maximum clock frequency at which the data path can operate is ______ $\text{MHZ}$.

Comments

What was given answer?? 14.28 MHz???

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no

i think it was it was 1000/35

Answer 1

The given circuit has two components:

1. (R₁, R₂) -> ADDER -> R₃
2. MUX -> R₅ -> R₆ -> R₄ -> MUX

When circuit operates in steady state component-1 will have a delay of 30 ns i.e. the maximum delay of its components (you can relate this with pipelining). But component-2 will have the delay of the sum of its components as it is a feedback circuit. Considering delay for R₅ and R₆ as Zero the delay for the circuit will be 25+10 = 35 ns.

Hence in order to operate this circuit, the clock delay should be at least 35 ns.

Hence, frequency = 1/35 x 10⁹ Hz = 28.57 MHz  .

Comments

$[R_{1}]+[R_{2}]\rightarrow R_{3}\Rightarrow 30+2=32 nsec$

$[R_{3}]\rightarrow [R_{4}]\Rightarrow 25$(using MUX)

for maximum frequency , we take minimum delay (as above), so max freq=1/66=$14.78MHz$

where i am wrong sir ?

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If you relate it with pipeline , this will be 2 stage pipeline 

R1 +R2 is buffer for stage 1 , adder is stage 1

=> 2 + 30 =32 ns

R3 +R4 is buffer for stage 2 ,  mux is stage 2

=> 10 + 25 =  35 ns

R5 + R6 are output buffer and R6 is given to mux input . it is called as Operand forwarding . it will not cause mux to wait for input .

To work each phase completely we required max time = 35 ns

So clock frequency = 1/35 ns = 28.57 MHz

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okk thank you sir :)

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I thought this qsn in this way:-

Select line of MUX will select either one of its input, so for maximum frequency we have to choose the path of minimum delay i.e $min(35,42)$

so frequency is $\frac{1}{35}$