0 votes 0 votes Please explain how the formula of frequency of clock obtained? Is the formula for time of clock not this -> Time of clock >= no of flip flop* delay per flip-flop? Also, does the formula change with type of clock? Digital Logic digital-logic + – agoh asked Jan 15, 2017 agoh 1.1k views answer comment Share Follow See all 4 Comments See all 4 4 Comments reply saurabh rai commented Jan 15, 2017 reply Follow Share ^see what r u talking about is applied on 2nd part of solution but here first we derive clock cycle time bcoz it is dependent of nand gate 0 votes 0 votes agoh commented Jan 15, 2017 reply Follow Share In the 2nd part, frequency of output is calculated. Its a different case, and that is fine. The doubt is related to formula of frequency of clock and its relation with gates and no of flip flops. 0 votes 0 votes saurabh rai commented Jan 15, 2017 reply Follow Share ^ frequency of clock depends on no. of nand gates nt on no of flip flops. bcoz clk cycle is generated using nand gates 0 votes 0 votes Rahul Jain25 commented Jan 15, 2017 reply Follow Share I think the Nand circuit is complementing the clk that is why we are dividing by 2, bcoz it is +triggered and therfore counter will change on +edge that will be after every two times propogation occurs through Nand circuit. 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes The Clock generator circuit is a Astable Multivibrator. If u give input as zero it takes N(no. of NAND gates)*tpd to get the output. For one complete Clock cycle it takes 2*N*tpd. Lakshmikanth P answered Jan 18, 2017 Lakshmikanth P comment Share Follow See all 0 reply Please log in or register to add a comment.