A DMA controller transfers 16 - bit word to memory using cycle stealing.
Hence, a word size = 16 bits and assume RISC processor, we have 1 Instruction size = 1 word = 16 bits.
The CPU is fetching and executing instructions at an average rate of 1 million instructions per second
CPU executes $1$ Million Instructions per second or we can say $1$ Million Words per second.
A DMA controller transfers 16 - bit word to memory using cycle stealing.
Hence, In $1$ cycle stolen from the CPU, DMA controller sends a word to memory. Device transmits $2400$ characters per sec where $1$ character = $8$ bit ASCII.
A). DMA controller is a special processor only used for DMA which acts as a intermediate between memory and I/O device.
As Device transmits $2400$ characters per sec, or $1200$ words per sec.
Now, $1$ word can be sent through Cycle Stealing in $1$ us or, $1$ cycle = $1$ us
Total cycles stolen to transfer $1200$ words = $1200$ cycles and a sec = $10^{6}$ cycles.
Hence, %age of cycles stolen = $\frac{1200}{10^{6}}$ = $0.12 %$
By how much will the CPU be slow down because of DMA transfer when the
characters are represented with 8 bit ASCII? --> 0.12 %
B).
when 32 –bit words are transferred to memory using cycle stealing
Now, Assume a word size = $32$ bits and so, DMA controller in $1$ cycle can send $4$ Bytes or $4$ characters.
Hence, $600$ words can be sent in $600$ cycles stolen by DMA.
Total cycles stolen to transfer $600$ words = $600$ cycles and a sec = $10^{6}$ cycles.
Hence, %age of cycles stolen = $\frac{600}{10^{6}}$ = $0.06 %$
By how much will the CPU be slow down because of DMA transfer when the
characters are represented with 8 bit ASCII? --> 0.06 %
