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Consider a pipelined processor with 5 stages (IF) Instruction Fetch , (ID) Instruction Decode and operand fetch, (PO) Perform Operation, (MA) Data Memory Access, (WB) Write Back. The IF, ID, MA and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 cycle for ADD and SUB instructions and takes 3 clock cycles for MUL instruction respectively. Operand forwarding from PO to ID and WB to ID )is used in the pipeline. The maximum number of stalls presents for any instruction in execution of following sequence of instruction is___________.

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R2 <--  R0+R1

R1 <-- R2-R1

R0 <-- R2-R0

R2 <-- R1*R0

R3 <--R1+R0

I/C 1 2 3 4 5 6 7 8 9 10 11
I0 IF ID PO MA WB            
I1   IF ID PO MA WB          
I2     IF ID PO MA WB        
I3       IF ID PO PO PO MA WB  
I4         IF ID X X PO MA WB

In this instruction Pipeline represent the Stall.

Hence Maximum no. of Stall = 2.

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