5 votes 5 votes Identify the mod value of the given riple counter 5 6 7 8 Digital Logic made-easy-test-series cbt-2017 digital-logic ripple-counter-operation + – pC asked Jan 22, 2017 • edited Mar 5, 2019 by adeebafatima1 pC 2.8k views answer comment Share Follow See all 42 Comments See all 42 42 Comments reply Show 39 previous comments Sushant Gokhale commented Jan 23, 2017 reply Follow Share @Debashish. Thats the flaw with the diagram. Again if you clear only the middle FF, then it will be mod-1 counter ,right? So, just assume for problem solving that all are cleared :P Dont kill me @Yash. After the falling edge of clock, the FF's enter 101 state. On level 1 of 5th clock pulse, FF's are still in state 100 and hence, NAND gate output is 1. 0 votes 0 votes yg92 commented Jan 23, 2017 reply Follow Share Ahh, @Debashish I got your point. Sorry in my case I am assuming the other two will be applied 0 directly instead of 1 making them clear at t5 along with Q1 0 votes 0 votes dd commented Jan 23, 2017 reply Follow Share in the morning I have posted one image...regarding this, after 5th falling edge if we wait for $\text{cycle-time/2}$ , for the next half high clock signal then NAND clears Q1. But Q1 is already $0$ in the last falling edge. SO no change, So can the overall state go to $<1,1,0>$ in the upcoming 6th falling edge ? 0 votes 0 votes Please log in or register to add a comment.
Best answer 3 votes 3 votes Importance of Preset and Clear Inputs in Flip-Flops and Usage https://www.youtube.com/watch?v=mXoQ4WAQ0qk Importance Points to be noticed when doing Aysnchronous Flip Flop Constructions https://www.youtube.com/watch?v=fKVZpupyP_o&index=186&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm Given Flip Flop Negative Edge Triggered . Output will change in falling edge No matter what the values of J and K is Whenever $\text{CLEAR} =0$ then Output $\text{Q} =0$ [Reset] Whenever $\text{PRESET} =0$ then Output $\text{Q} =1$ [Set] Hence the output sequence is $0-1-2-3-4-7-6-7-0$ pC answered Jan 23, 2017 • selected Jan 23, 2017 by Sushant Gokhale pC comment Share Follow See all 15 Comments See all 15 15 Comments reply Show 12 previous comments Sushant Gokhale commented Jan 23, 2017 reply Follow Share bubble and (preset or preset bar) -> Qn = 1 When bubble, input should be 0. 0 votes 0 votes Sushant Gokhale commented Jan 24, 2017 reply Follow Share @pc. I think it should be mod 7 counter. I started from 111. So, the outputs for Q0 - Q1 - Q2 will be: 111 000 100 010 110 001 001 Now, 001 is stable for 1/2 cycle of clock. But, this output is stable. So, its mod-7 counter. 0 votes 0 votes vaishali jhalani commented Jan 24, 2017 reply Follow Share Yes..I am also getting mod 8. But in solution it is given that at 6th clock output is 111, I am not getting this. 0 votes 0 votes Please log in or register to add a comment.