My Approach:
Default in previous years Gate it has been observed that without pipelining we assume the split phase scenerio. The WB stage will write the output during rising edge of clock and ID stage will fetch at the falling edge of clock. Hence, WB and ID stage can overlap in “without-pipelining”. The number of clock cycles will be
14 – without pipelining
9 - with pipelining ( Which is correct in Skraj's solution )
Hence Ans – 14-9 = 5
Without Pipelining :
|
1
|
2
|
3
|
4
|
5
|
6
|
7
|
8
|
9
|
10
|
11
|
12
|
13
|
14
|
I1
|
F
|
D
|
X
|
M
|
W
|
|
|
|
|
|
|
|
|
|
I2
|
|
F
|
|
|
D
|
X
|
M
|
W
|
|
|
|
|
|
|
I3
|
|
|
|
|
F
|
|
|
D
|
X
|
M
|
W
|
|
|
|
I4
|
|
|
|
|
|
|
|
F
|
|
|
D
|
X
|
M
|
W
|