1 votes 1 votes CO and Architecture pipelining data-hazards co-and-architecture + – biranchi asked Jan 24, 2017 retagged Nov 13, 2017 by Arjun biranchi 2.0k views answer comment Share Follow See all 6 Comments See all 6 6 Comments reply dd commented Jan 24, 2017 i edited by dd Jan 24, 2017 reply Follow Share what is the answer given ? I think 2 0 votes 0 votes thor commented Jan 24, 2017 reply Follow Share What does LW R2,0(R1) mean? 0 votes 0 votes Digvijaysingh Gautam commented Jan 24, 2017 reply Follow Share I also think 4 RAW dependencies:- 1) I1-I2 2) I1-I3 3) I1-I4 4) I2-I4 5) I3-I4 but out of these I1-I4 cannot be hazard becoz I3 is writing in R1 4 votes 4 votes Gaurab Ghosh commented Jan 27, 2017 reply Follow Share Why 2? Debashish Deka Getting 4 hazards 0 votes 0 votes Shubham Sharma 2 commented Sep 28, 2017 reply Follow Share @thor LW R2,0(R1) means add 0 to R1 and load it in R2. LW is Load Word.. 0 votes 0 votes susmit600 commented Feb 10, 2021 reply Follow Share I1 – I3 won’t be a hazard since any hazard involving I1 is resolved by a stall during I2. There is a data dependency between I1 and I3, but no hazard. Answer should be 2. 0 votes 0 votes Please log in or register to add a comment.
2 votes 2 votes RAW hazards:- 1) I1-I2 2) I1- I3 3) I2-I4 4) I3-I4 Option C should be correct. Shubham Sharma 2 answered Mar 11, 2017 edited Sep 28, 2017 by Shubham Sharma 2 Shubham Sharma 2 comment Share Follow See all 6 Comments See all 6 6 Comments reply Show 3 previous comments Shubhanshu commented Sep 28, 2017 reply Follow Share but it is not necessary that raw hazards occur between two adjacent instruction. ryt??? 0 votes 0 votes Shubham Sharma 2 commented Sep 28, 2017 reply Follow Share @Shubhanshu ryt. As data hazards occur when instructions that exhibit data dependence, modify data in different stages of a pipeline. 0 votes 0 votes sachin486 commented Jul 30, 2020 reply Follow Share dont confuse raw dependency with raw hazard .... if raw dependency cause pipeline to stall then it will be count as raw hazard. here instruction 2 has stall of 2 cycle due to raw dependency on I-1 and I-4 also cause 2 stalls due to raw dependency on I-3 so total 4 hazard option c is correct 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Answer should be 2 In RAW hazard or true data dependency we see for dependency between adjacent instructions only.. I.e. I1- I2 AND I3- I4 vamp_vaibhav answered Sep 27, 2017 vamp_vaibhav comment Share Follow See 1 comment See all 1 1 comment reply Shubhanshu commented Sep 28, 2017 reply Follow Share @vamp_vaibhav read this:- https://courses.cs.washington.edu/courses/cse378/09au/lectures/cse378au09-15.pdf 0 votes 0 votes Please log in or register to add a comment.