Question

Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.97, but increase access time to 1.5 ns. What conditions must be met for this change to result in improved performance?

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plzz add more in this answer and correct the  answer if wrong......

when we increase the hit ratio than the acces time is increased as given in the question..

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i think we should use direct mapped cache...and we should increase the size of the cache as.. in direct cache  we need address...to  identify the particular word.....so it easy to get word in less time due to avalibility of address...

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but if we use associative cache than there is no need of address and so we have to search throught the cache which wiill increase the cache accees time ..and performance will decreases.....

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Comments

Actually associativity is not doing a linear search. For say 4-way associativity all 4 are compared in parallel. So, though it is not as fast as direct mapped, it is only slower by a small factor.

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means in associative cache also  there is presence of comparator which will compare all the cache lines with cpu generated address if there is no linear search... ?

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yes..

Answer 1

The question says that increasing the cache size results in better hit rate and more access time. So, we need not think about how this is achieved (direct or associative) but just give the equation for access time. Assuming simultaneous access: (by default take hierarchical)

$T_{avg} = 0.95 \times 1 + 0.05 \times T_{mem}$

$T_{avg}^{new} = 0.97 \times 1.5 + 0.03 \times T_{mem}$

$T_{avg}^{new} < T_{avg} \implies \\ 0.97 \times 1.5 + 0.03 \times T_{mem} < 0.95  + 0.05 \times T_{mem} \\ T_{mem} > \frac{0.505}{0.02} = 25.25 ns$

For hierarchical access:

$T_{avg} = 1 + 0.05 \times T_{mem}$

$T_{avg}^{new} = 1.5 + 0.03 \times T_{mem}$

$T_{avg}^{new} < T_{avg} \implies \\1.5 + 0.03 \times T_{mem} < 1 + 0.05 \times T_{mem} \\ T_{mem} > \frac{0.5}{0.02} = 25 ns$

Comments

Quoting you: 

"For hierarchical access: Tavg = 1 + 0.05* Tmem"

Why are we considering 0.05 for Tmem?

Should it not just be Tmem, since if cache is missed then only MM should be accessed,

but Tmem will be considered wholly, not in the miss factor?

Tavg=1+0.05×TmeTavg=1+0.05×Tmem

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Sir what sort of access architecture should we assume if such question comes up in gate.

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Assume hierarchical for read unless told so.