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Kathleen asked Sep 23, 2014
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GATE CSE 1999 | Question: 1.21
The maximum gate delay for any output to appear in an array multiplier for multiplying two $n$ bit numbers is $O(n^2)$ $O(n)$ $O(\log n)$ $O(1)$
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Kathleen asked Sep 16, 2014
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GATE CSE 2003 | Question: 11
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is $\Theta(1)$ $\Theta(\log n)$ $\Theta(n)$ $\Theta(n^2)$
Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is$\Theta(1)$$\Theta(\lo...
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prajjwal_191 asked Dec 9, 2023
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Doubt in NAND and NOR gate.
Why NAND gate is preferred over NOR gate?
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adil.wadood asked Jul 3, 2018
546 views
General Topic Doubt Digital Logic: Min No Gates
What are the minimum number of nand or nor gates required for 2 bit adder ( ie. 4 input A,B,C,D) ?
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