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Sajal Mallick asked Nov 23, 2023
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Madeeasy ots Digital Logic Combinational Circuits
I am confused in active low enable input and active low output?
I am confused in active low enable input and active low output?
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Sajal Mallick asked Nov 20, 2023
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How to solve this?
How to solve this?
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Sajal Mallick asked Nov 20, 2023
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Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is different.
Here clr is active low that means 0 then it will clear to 0. Then (Q2.Q0)' =0 or Q2=1 and Q0=1 then clr works. Then it will contain only 1 state. Right?? But answer is ...
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Sajal Mallick asked Nov 19, 2023
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madeeasy ots digital logic
In the 2nd cycle as it is ripple counter Q0 will change and it will 0 so for that reason Q1 will not get clock and it will be in previous state that is 1. So output should be 01. Right??
In the 2nd cycle as it is ripple counter Q0 will change and it will 0 so for that reason Q1 will not get clock and it will be in previous state that is 1. So output shoul...
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