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A byte addressable computer has a small data cache capable of holding 16 32 bit words. Each cache capable of holding 16 32 bit word. Each cache block consists of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache  is used is ___________ ?

                100, 104, 108, 104, 107, 108, 105, 102, 108, 103.

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Each cache is capable of holding 16 32 bit word.

Here its a byte addressable so word is a byte .

So on the basis above 

Cache size= 16 * (32/8) = 16 *4 = 64 words( byte ).

A single cache block consists of 32 bit words (32/8) = 4 words .

No of block (cache lines ) = 64W/4W = 16 lines 

It is said it is 4 way set associative mean we have 4 block or lines in a set .

4 lines in 1 set 

so 16 lines will be 4 set 

Hence cache organization goes like this 

TAg = (6 - (2+2))= 2  bits 

Set = 2 bits 

Block offset is 2 bits 

So cache line from Line 0 to line 2 will be in set 0 

Line 4 to line 7 will be in Set 1 

Line no 8 to line no 11 will be in set 2

Line no 12 to line no 15 will be in set 3

Now they have specifie dall the hexadecimal address you need to convert into each one of them to decimal address 

and mapped into required to any line of the required set .

Hence we get 

SET 0 :

Line no 0 = 100

line no 1 = 104 

line no 2 =108

Line no 3 :

SET 1
Line 4 = 105 

Line 5

Line 6 

Line  7 

SeT 2

Line no 8 = 102 

Line no 9 

Line no 10 

line no 11 

SET 3

Line 12 = 107 

Line 13 = 103

Line no 14 

Line 15 :

hence miss ratio is no of miss / toatl no of references = 7 /10 = 0.7 

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