7 votes 7 votes Digital Logic digital-logic + – Anusha Motamarri asked Feb 6, 2017 Anusha Motamarri 3.3k views answer comment Share Follow See all 29 Comments See all 29 29 Comments reply Show 26 previous comments Pankaj Joshi commented Feb 9, 2017 reply Follow Share I think we should answer 120 as Arjun sir said its conceptually correct at least then we can challenge the answer sheet if they solved it differently 0 votes 0 votes Arjun commented Feb 9, 2017 reply Follow Share @Anusha If the question is like that then we should see when the output stops changing. 0 votes 0 votes aakashpreetam commented May 24, 2018 reply Follow Share This is the actual GATE Question, all are Full Adders Answer given is 50 in the Key https://drive.google.com/file/d/0ByPcpxjSfRuVVWd4c184YWJuUEk/view https://drive.google.com/file/d/0ByPcpxjSfRuVTldxaDBWUE45ZE0/view 0 votes 0 votes Please log in or register to add a comment.
4 votes 4 votes Delay for sum is 2*XOR = 2*20 = 40ms Delay for carry is 1xor+1and+1or=20+15+10=45 ns in ripple-carry adder each adder must wait for the full output from the previous adder. hence delay for S3= 3*45+40=175 ns delayfor last carry= 4*45=180 ns nd it is asking for stable o/p so it should b 180 ns . saurabh rai answered Feb 6, 2017 edited Feb 6, 2017 by saurabh rai saurabh rai comment Share Follow See all 6 Comments See all 6 6 Comments reply Show 3 previous comments target2017 commented Feb 6, 2017 reply Follow Share for first bit there is no carry input, can we use half adder only for first bit? 0 votes 0 votes saurabh rai commented Feb 6, 2017 reply Follow Share @anusha i think u r right .... edited 0 votes 0 votes Namit Dhupar commented Nov 6, 2017 reply Follow Share You could have made the answer more simple! 0 votes 0 votes Please log in or register to add a comment.
3 votes 3 votes If XOR= 20 AND= 15 OR=10 Shouldn't the answer be 4*45=180ns? Vijay Thakur answered Feb 6, 2017 Vijay Thakur comment Share Follow See all 2 Comments See all 2 2 Comments reply rahul sharma 5 commented Feb 7, 2017 reply Follow Share Where is OR gate in the figure?Are we referring to same figure given above? And what is 10 ns delay for OR?I dont see it is mentioned in question? Please help 0 votes 0 votes Anusha Motamarri commented Feb 7, 2017 reply Follow Share they gave XOR gate by mistake in the figure. to get carry we shud use OR gate ryt? and there are 3 delays given.. we assumed the 3rd delay to be OR gate delay 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes The question is straight out of Salivahanan! So the stable output is generated by the last carry bit C4 = 4 * Tp, the in this 4 bit binary adder, as the propagation delay is clearly (20+15+10)nsec = 45nsec so,C4 = 4 * 45 = 180nsec Namit Dhupar answered Nov 6, 2017 Namit Dhupar comment Share Follow See all 0 reply Please log in or register to add a comment.
0 votes 0 votes The answer should be 50 ns. Amit puri answered Aug 29, 2018 edited Aug 30, 2018 by Amit puri Amit puri comment Share Follow See all 0 reply Please log in or register to add a comment.