Nothing is given about the OR gate so, lets consider its delay as 0.
And at time=0 ns, a,b and c are applied to the input.
Now at time t=12ns (delay of AND 2 gate), We will have output bc from AND2 gate, and some output (does not matter) from final OR gate.
Complement of b will be input of AND 1 gate at time =9 nsand b'a comes as output of AND1 gate at t=19ns.
At t=19 ns, output bc+b'a comes from final OR gate.
So, time difference between correct output and first output is 19ns-12ns=7ns