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Consider 6 stage pipeline (S1S2S3S4S5S6) which allows all the instructions except branch instructions. Processor stops fetching the following instruction after the branch until the target address is available. Target address is available in the S4 stage. Program contain 40% of branch instructions. All the stages are balanced with a 2.3 GHz clock. MIPS rate of the processor is ________ (in 2 decimal places).

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Best answer
4 votes
4 votes

As target address is available after S4 stage, 

So, stall cycle is 3

stall frequency =40%

cycle time=$\frac{1}{2.3\times 10^{9}}$=.435 ns.

So, proceesing time= (1+stall cycle$\times$stall frequency)$\times$cycle time

                            =(1+3$\times$4)$\times$0.435=0.957ns=1044.9MIPS

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3 votes
3 votes

Here we need to find the CPI of each instruction in pipelined system..

So we know :

CPIpipeline   =  CPIideal pipeline   +    No of stalls / instruction

Now here stall is due to branch instruction...

So branch penalty  = Stage at which target address is found - 1

                            = 4 - 1

                            = 3

Fraction of branch instruction  =  0.4

Hence CPI            =  1 (CPI of ideal pipeline)  + 0.4 * 3

                            =  2.2

Hence time taken by 1 instruction  =  CPI * Cycle time

                                                   =  CPI / Clock frequency

                                                   =  2.2 / ( 2.3 * 109 )  s

So no of instructions / sec             =  (2.3 * 109)  /  2.2

     no of million ins / sec               =   (2.3 * 1000) / 2.2

                                                   =   1045.46 MIPS

NOTE : wrong calculation by madeeasy

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