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Consider 1000 instructions
Number of memory references for 1000 intructions= 1.4*1000=1400

Out of these 1400 references to memory, 0.1% have a miss in L1 cache level = 0.1*1400=140

Thus 140 memory references go to level 2 of cache.

We know there are 7 misses for 1000 instruction in L2 and 140 references happen to L2
Therefore miss rate = 7/140=0.05

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