edited by
13,566 views
39 votes
39 votes

When two $8\text{-bit}$ numbers $A_{7}\cdots A_{0}$ and $B_{7}\cdots B_{0}$ in $2$'s complement representation (with $A_{0}$ and $B_{0}$ as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are $S_{7}\cdots S_{0}$ and the carry bits are $C_{7}\cdots C_{0}$. An overflow is said to have occurred if

  1. the carry bit $C_{7}$ is $1$
  2. all the carry bits $\left ( C_{7},\cdots ,C_{0} \right )$ are $1$
  3. $\left ( A_{7} \cdot B_{7} \cdot \overline{S_{7}}+\overline{A_{7}} \cdot \overline{B_{7}} \cdot S_{7} \right )$ is $1$
  4. $\left ( A_{0} \cdot B_{0} \cdot \overline{S_{0}}+\overline{A_{0}} \cdot \overline{B_{0}} \cdot S_{0} \right )$ is $1$
edited by

6 Answers

Best answer
42 votes
42 votes

Answer is (C)

Overflow is said to occur in the following cases
$$\begin{array}{|c|c|c|} \hline C_{7} & C_{6} &\text{Overflow} \\\hline0&0&  \text{NO}\\ 0&1& \text{YES} \\  1&0&\text{YES} \\ 1&1&\text{NO}  \\\hline \end{array}$$
The $3^{\text{rd}}$ condition occurs in the following case $A_{7}B_{7}S_{7}',$ now the question arises how? 
$$\begin{array}{|c|c|c|} \hline C_{7} & C_{6} \\\hline  A_{7} &1\\\ B_{7} &1 \\ S_{7} & 0  \\\hline \end{array}$$

NOW, $A_{7}=1$ AND $B_{7}=1, S_{7}=0$ is only possible when $C_{6}=0$ otherwise $S_{7}$ would become $1$.

$C_{7}$ has to be $1 (1+1+0$ generates carry$)$

ON similar basis we can prove that $C_{7}=0$ and $C_{6}=1$ is produced by $A_{7}'B_{7}'S_{7}$. Hence, either of the two conditions cause overflow. Hence (C).

Why not A? when $C_{7}=1$ and $C_{6} =1$ this doesn't indicate overflow ($4^{\text{th}}$ row in the table)

Why not B? if all carry bits are $1$ then, $C_{7}=1$ and $C_{6}=1$ (This also generates $4^{\text{th}}$ row)

Why not D? These combinations are $C_{0}$ and $C_{1}$, the lower carrys do not indicate overflow

edited by
56 votes
56 votes
19 votes
19 votes

Observe one thing, Overflow can occur when we add two negative numbers or two positive numbers. When we add one negative and one positive number, there can't be an overflow.

Now when we add two positive numbers, result should always be positive and when we add two negative numbers, result should be negative, In representation of signed binary numbers, MSB represents sign of number.

1. Now if MSB of both input numbers is 1 (means numbers are negative) but MSB of sum is 0 (means sum is positive) then it means there is an overflow.

2. Similarly, when MSB of both inputs is 0 (means numbers are positive), but MSB of sum is 1 (means sum is negative), then it also indicates overflow.

Statement 1 above indicates, A'7B'7S7 is 1. Statement 2 above indicates A7B7S'7 is 1.

Hence Option C is answer

5 votes
5 votes

the solution is  C)

if Both A7 and B7 is 1 then C7 will be 1 and S7 is 0 means C6 is 0 hence C7.C6'

if Both A7 and B7 is 0 then C7 will be 0 and S7 is 1 means C6 is 1 hence C7'.C6

hence combining both we get C7.C6'+C7'.C6

which is C7 XOR C6 which is condition of detecting  Overflow

Answer:

Related questions

45 votes
45 votes
4 answers
3