edited by
19,456 views
62 votes
62 votes
A cache memory unit with capacity of $N$ words and block size of $B$ words is to be designed. If it is designed as a direct mapped cache, the length of the $\textsf{TAG}$ field is $10$ bits. If the cache unit is now designed as a $16$-way set-associative cache, the length of the $\textsf{TAG}$ field is ____________ bits.
edited by

10 Answers

Best answer
87 votes
87 votes

In set-associative 1 set = 16 lines. So the number of index bits will be $4$ less than the direct mapped case.

So, Tag bits increased to $14$ bits.

edited by
79 votes
79 votes

hope it helps!!!

edited by
47 votes
47 votes

Cache capacity =N words

Block size= B words,bits for block offset=log(B)

No of lines in Direct  Mapped cache =N/B,bits for no. of lines=log(N/B)

No of Sets in 16-way set associative cache=N/16B,,bits for no. of sets=log(N/16B)

In direct mapped length of tag =10 bits

Length of PHYSICAL ADDRESSES :-

DIRECT-MAPPED
TAG-10 LINE.NO:-LOG(N/B) BLOCK OFFSET:-LOG(B)
16-WAY SET ASSOCIATIVE
TAG-X SET.NO-LOG(N/16B) BLOCK OFFSET:-LOG(B)

As Physical address is same for both cache mappings,

10+LOG(N/B)+LOG(B)=X+LOG(N/16B)+LOG(B)

10+LOG(N/B)=X+LOG(N/16B)                              //AFTER CANCELLING LOG(B) 

2^(10+LOG(N/B))=2^(X+LOG(N/16B))                 //EXPONENTIATION WITH 2 ,BOTH SIDES

(2^10) *(N/B)=(2^X) *(N/16B)

(2^10) =(2^X) *(1/2^4)

2^14=2^X

X=14                                                                 //APPLYING LOG TO BOTH SIDES

13 votes
13 votes
in Direct mapping length is 10 bits that means at each index of cache 2^10 lines can be mapped

after 16 way set associative....16*(2^10) lines can be mapped in each set so total 2^14 lines hence tag bit must be able to address these many lines so 14 bits required

answer is 14 bits
Answer:

Related questions