2 votes 2 votes For a $10$-bit digital ramp ADC using $500\;\text{kHz}$ clock, the maximum conversion time is $2048\; \mu \;\text{S}$ $2046\; \mu \;\text{S}$ $2064\; \mu \;\text{S}$ $2084\; \mu \;\text{S}$ Digital Logic isro2016-ece digital-logic + – sh!va asked Feb 21, 2017 • edited Dec 4, 2022 by Lakshman Bhaiya sh!va 1.8k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
1 votes 1 votes The answer for the above question is B) 2046uS Solution: (2ⁿ-1)*clock speed(2us)=2046uS Nishanth answered Apr 30, 2017 Nishanth comment Share Follow See all 0 reply Please log in or register to add a comment.