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ISRO2013-ECE Digital Logic

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What is the frequency and duty cycle of output $\text{Y},$ when CLK frequency is $\text{1MHz} \;@\; 50\%$ duty cyle?

  1. $500 \;\text{KHz} \;@\; 50\%$ duty cycle
  2. $500 \;\text{KHz} \;@\; 25\% $duty cycle
  3. $250 \;\text{KHz} \;@\; 50\%$ duty cycle
  4. $250 \;\text{KHz} \;@\; 25\%$ duty cycle
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It is synchronous circuit and first FF is + edge triggered and other is - edge triggerred. Timing diagram is, 

Now in the above diagram clearly output has double the time period of clock pulse which means frequency is half. So output frequency is 500 kHz and also in a single period output is in set condition on 25% of time so it has 25% duty cycle. So answer is option B).

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