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Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).

add r1,r2,r3       // r1 = r2+r3
sub r4,r1,r3      //r4 = r1 - r3
mul r5,r2,r3     // r5 = r2*r3

Identify the possible pipeline hazard and the affected instruction.

  1. Read after write hazard during mul
  2. Read after write hazard during sub
  3. Read after write hazard during add
  4. Write after write hazard during mul
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RAW hazard means you write operand value into a register at instruction i and you read the same register in further instruction.
Here value is written to r1 in add
and value is read from r1 in sub
because of that in sub the next instruction cannot execute in the following clock cycle
if sub cannot be executed in immediate clock cycle until add is fully executed
This is known RAW hazard

So, answer is option b
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