Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).
add r1,r2,r3 // r1 = r2+r3
sub r4,r1,r3 //r4 = r1 - r3
mul r5,r2,r3 // r5 = r2*r3
Identify the possible pipeline hazard and the affected instruction.
- Read after write hazard during mul
- Read after write hazard during sub
- Read after write hazard during add
- Write after write hazard during mul