Consider a computer with the following features:
90% of all memory accesses are found in the cache (
hit ratio = 0.9);
The block size is
2 words and the whole block is read on any miss;
The CPU sends references to the cache at the rate of
107 words per second;
25% of the above references are writes (writes = 25%, reads = 75%);
The bus can support
107 words per second, read or writes (total bus bandwidth =
107);
The bus reads or writes a
single word at a time;
Assume at any one time,
30% of the block frames in the cache have been modified;
The cache uses
write allocate on a write miss.
Calculate the percentage of the bus bandwidth used on the average if cache is WRITE BACK: