3 votes 3 votes Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is (a) 4 (b) 5 (c) 6 (d) 7 Digital Logic isro-ece digital-logic + – sh!va asked Mar 2, 2017 • retagged Mar 9, 2019 by Naveen Kumar 3 sh!va 7.1k views answer comment Share Follow See 1 comment See all 1 1 comment reply srestha commented Mar 2, 2017 reply Follow Share ans 6? 0 votes 0 votes Please log in or register to add a comment.
Best answer 6 votes 6 votes Option C)- 6 NAND Rahul Jain25 answered Mar 2, 2017 • selected Mar 2, 2017 by sh!va Rahul Jain25 comment Share Follow See all 5 Comments See all 5 5 Comments reply Show 2 previous comments sh!va commented Mar 3, 2017 reply Follow Share Ok.. So most correct approach is to convert given equation to complimented AND format?? like you did in this question?! 0 votes 0 votes sh!va commented Mar 3, 2017 reply Follow Share @rahul: Can you have a look in this question also? https://gateoverflow.in/120389/isro-2007-ece-half-adder-using-nand 0 votes 0 votes Rahul Jain25 commented Mar 3, 2017 reply Follow Share Yes most probably complement and then see how we can minimize, also I have answered the question you commented, it is also one of the known and good method to solve such question. 1 votes 1 votes Please log in or register to add a comment.
0 votes 0 votes 6 "2 input NANA" gates needed"_ Prateek kumar answered Jan 9, 2018 Prateek kumar comment Share Follow See all 0 reply Please log in or register to add a comment.