0 votes 0 votes A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be a) 25 ns b) 50 ns c) 75 ns d) 100 ns Digital Logic isro-ece digital-logic + – sh!va asked Mar 3, 2017 retagged Mar 9, 2019 by Naveen Kumar 3 sh!va 6.2k views answer comment Share Follow See 1 comment See all 1 1 comment reply Priyankamishra commented Nov 12, 2018 reply Follow Share @arjun sir @vikram sir please explain why are we not taking mod*tin here? 0 votes 0 votes Please log in or register to add a comment.
4 votes 4 votes It is synchronous counter all FF's will be clocked simultaneously so delay will be equal to delay of one FF = 25 ns Rahul Jain25 answered Mar 3, 2017 Rahul Jain25 comment Share Follow See 1 comment See all 1 1 comment reply sumit_kumar commented Apr 16, 2018 reply Follow Share I m confused if it is minimum time or maximum time.....before 25 ns output is not available then how this is maximum time to change state ? Will Output not change only after 25 ns ? 0 votes 0 votes Please log in or register to add a comment.