Register

ISRO 2007-ECE Memory

• retagged by
4,515 views
0 votes
0 votes
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is

a) 2

b) 4

c) 8

d) 16
• retagged by
User Avatar

1 Answer

Voting & Accepting an answer helps improve the community
← PreviousNext →
← Previous in categoryNext in category →

Related questions

0 votes
0 votes
1 answer
2
sh!va asked Mar 3, 2017
458 views
ISRO 2007- ECE Time division MUX
In time division multiplexing a) Time is doubled between bits of a byte b) Time slicing at CPU level takes place c) Total time available in the channel is divided between several users and each users is allotted a time slice. d) None of the above
In time division multiplexinga) Time is doubled between bits of a byteb) Time slicing at CPU level takes placec) Total time available in the channel is divided between se...
User Avatar
0 votes
0 votes
1 answer
3
sh!va asked Mar 1, 2017
656 views
ISRO 2008-ECE Cache Memory
The advantage of write (copy) back data cache organization over write through organization is (a) Main memory consistency (b) Write allocate on write miss (c) Less memory bandwidth (d) Higher capacity requirement
The advantage of write (copy) back data cache organization over write through organization is(a) Main memory consistency(b) Write allocate on write miss(c) Less memory ba...
User Avatar
0 votes
0 votes
1 answer
4
sh!va asked Feb 28, 2017
404 views
ISRO 2010-ECE Cache memory
A microprocessor has a cache memory with access time of 2 ns and a main memory with access time of 10 ns. If the cache miss ratio is 0.6, what is the average memory access time? a) 6.8 ns b) 6 ns c) 5.2 ns d) 12 ns
A microprocessor has a cache memory with access time of 2 ns and a main memory with access time of 10 ns. If the cache miss ratio is 0.6, what is the average memory acces...
User Avatar
Link Copied!