1 votes 1 votes A 4 bit module -16 ripple counter uses JK F/F. If the propagation delay of each F/F is 50 nano seconds, the maximum clock frequency that can be used is equal to (a) 20 MHz (b) 5 MHz (c) 10 MHz (d) 4 MHz Digital Logic isro-ee digital-logic + – sh!va asked Mar 10, 2017 • retagged Mar 7, 2019 by Naveen Kumar 3 sh!va 1.5k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 1 votes 1 votes Total delay in ring counter is nFF × Tdelay = 4 × 50 = 200 ns. So maximum clock frequency is 1/(200 × 10-9) = 5 × 106 Hz = 5 MHz (option B) Rahul Jain25 answered Mar 10, 2017 • selected Mar 13, 2017 by Rahul Jain25 Rahul Jain25 comment Share Follow See 1 comment See all 1 1 comment reply Kaluti commented Mar 12, 2017 reply Follow Share It is a ripple counter having 2^(n) states so number of flip flop will be 4 so propagation delay would be 4*250 ns so frequency would be 1/(200*10^(-9)) comes out to be 5 mega hertz 0 votes 0 votes Please log in or register to add a comment.
