i suppose the questions says there is a single memory for data and instruction. obviously data hazard is there the third instruction will suffer from data hazard because during that clock period R1,R2 has not be written by the first two instruction structural hazard is also there Look at the last instruction it access memory to write the value from R1 but the next instruction can be an instruction which will be fetched from memory so there will be issue regarding hardware resource(memory) control hazard wont be a possible as there or no jump or branch instructions so to conclude this pipeline has got data and structural hazard option D