A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses:
- F-stage — instruction fetch (9 ns),
- D-stage — instruction decode and register fetch (3 ns),
- X-stage — execute/address calculation (7 ns),
- M-stage — memory access (9 ns),
- W-stage — write back to a register (2 ns).
Assume that for each stage, the pipeline overhead is 1 ns. A program P having 100 machine instructions runs on M, where every 3rd instruction needs a 1-cycle stall before the X-stage. Calculate the CPU time in seconds for completing P.