Firstly there is no systematic approach to find the minimum number of Gates required, you have to be efficient in utilising the boolean algebra laws.
And one thing you can observe that for SOP implementation AND-OR implementation is used which is same as NAND-NAND implementation.
Now in the given function, f=a'b+ b'c+ cd'.
You can take c common from 2nd, 3rd term to get c(b'+d').
Again notice that b'+d' =(bd)' [by de-Morgans law]
Thus your given expression becomes f=a'b+ c(bd)'.
Now,
a' will take 1 NAND Gate.
feed a'b into 1 NAND gate. ---(1)
(bd)' will take 1 NAND gate.
Feed c(bd)' into 1 NAND gate.-----(2)
Lastly, feed (1),(2) into 1 more NAND gate to obtain f.
Finally the minimum number of NAND gates require: 5