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Assume the following performance characteristics on a cache read miss: one clock
cycle to send an address to main memory and four clock cycles to access a 32-bit word
from main memory and transfer it to the processor and cache.

 What is the miss penalty if the cache line size is four words and a transfer is executed,
with one clock cycle per word transfer?
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Miss means a word is not found in cache and the Miss Penalty would be the number of cycles required to transfer the block (containing word) from memory to cache.

Since cache line is of four words, so when a miss happens four words from the memory would have to be transferred to the cache.

Memory is word addressable. This means at each address, a word (of 32-bit) is stored.

To get a word (of 32-bit) from memory, we would have to send an address to memory from where word is to be retrieved and then transfer the word so obtained to the cache. And we would need to do this four times, because cache line size if of four words.

Sending an address to memory requires $1$ cycle, while transferring a word (obtained by providing address) from memory to cache takes 4 cycles. So total $5$ cycles needed to transfer a word from memory to cache.

Doing this four times would require $5*4$ = $20$ cycles

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