Implementation of BSA(Branch and save address) instruction

Question

I have a doubt regarding the implementation of BSA instruction.

I read that BSA instruction can be implemented as :-

T4:-    m[AR] <-- PC;   AR<--AR+1

T5:-    PC<--AR; SC<--0

Here T4 and T5 are 4th and 5th clock cycles respectively. AR is address register and SC is sequence counter.

My doubt is how can both m[AR]<--PC and AR<--AR+1 execute together at one clock cycle (T4) ? . Incrementing AR can happen before and that can cause changes to the position where PC is written. So they should happen at different clock cycles right so that they can execute in proper order?

Comments

We are saving only the return instruction addr in memory then What is the state of SC after return ?

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m[AR] <-- PC - This is a memory write operation, and its not positive edge triggered.   ie, it could be performed at any time. The time required to execute it will depend on the memory write time, and it will be less than 1 clock cycle. So it will get finished before that clock cycle(T4).

AR<--AR+1 - This is an increment operation in AR register, and all register operations (load, increment etc) are positive edge triggered. So, it will get executed only at the end of that clock cycle (T4)

As a result both could be done in T4 itself without any problem

Answer 1

m[AR] <-- PC - This is a memory write operation, and its not positive edge triggered.   ie, it could be performed at any time. The time required to execute it will depend on the memory write time, and it will be less than 1 clock cycle. So it will get finished before that clock cycle(T4).

AR<--AR+1 - This is an increment operation in AR register, and all register operations (load, increment etc) are positive edge triggered. So, it will get executed only at the end of that clock cycle (T4)

As a result both could be done in T4 itself without any problem

Comments

Thanks for your answer. Yes, you are correct that memory operation is not positive edge triggered and hence can happen anywhere in clock cycle T4 .

However, we are scheduling it in clock cycle T4. So how will you make sure that AR increment happens only at the "end" and memory operation at the start ? Is there any mechanism to control it ? Even at the start of a clock cycle we have a positive edge triggered edge, why can't increment operation take place at that time ?

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Actually a clock has only 1 positive and 1 negative edge (as shown in the image)

Answer 2

since all micro operations are +ve edge triggered, at the beginning of 4th clock cycle addr from AR is given to memory , READ control signal of memory and INR control signal of AR gets active. But the actual increment takes place at next clock transition.

Comments

Thanks for answering . I still don't understand how are you sure that at the beginning m[AR] and not increment operation is executed? Both are positive edge triggered operation and any of them can occur at the beginning right? (At the beginning of every clock cycle the clock value goes from 0 to 1 that is positive edge triggered)

Answer 3

After T3 we have realized that it is Memory Reference and at T2 PC = PC + 1;
At T4 that is BSA has been executed and AR register contain the memory location just above the subroutine.

so m[AR] <-- PC; you saving the return address to the memory. (which is the PC of T2 state).
and then incrementing the AR = AR + 1 ( because to fetch the memory you need AR ) as you move next consecutive memory location to execute the subroutine by setting PC = AR in the T5.

Hope this help.

Comments

i didn't get u r explanation can u explain in a simple waay plzzzzz

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http://home.adelphi.edu/~siegfried/cs371/371l10.pdf

this might help.