The hardware of the RISC-style processor is divided into 5 execution stages: IF, ID, EXE, MA, WB.
(a) In the first part, the question is telling that the memory access (for IF and MA stage) is completed in one single clock cycle. Hence, each of the above four classes of instructions would be executed in exactly five steps each taking 1 CC.
Taking total 100 instructions in the program,
20 branch instruction would take time = 20 * 5 * 1CC time. (CC = clock cycle)
Given, 1CC time = 1/1GHz = 1ns.
So, this 20 branch instructions would take 100ns to execute.
Similarly, 20 Load instructions would take 100ns, 10 Store instructions would take 50ns, 50 ALU based instructions would take 250ns to complete its execution.
In total, all this 100 instructions would take (100 + 100 + 50 + 250)ns = 500ns.
So, rate of instruction execution = 100 instructions/500ns = 0.2 Giga instructions/sec.
(b) In this part, question is saying that 90% of instruction takes 1CC for the IF stage whereas, 10% of instructions take 4CC for the IF stage. Additionally, all the Load and Store instructions take 3CC for MA stage.
Beacuse of this, the average time/instruction would increase and the instructions/sec would decrease.
From part – (a), the execution time for IF-stage of 10% instructions would ‘increase’ by 3CC because previously it took 1CC, so now it would take 3 + 1 = 4CC.
Similarly, execution time for MA-stage of all Load and Store instructions would ‘increase’ by 2CC because previoulsy it took 1CC, so now it would take 2 + 1 = 3CC.
So, total time to execute 100 instructions would be = 500ns (from part – (a)) + 10 * 3CC + (20 + 10) * 2CC = 500ns + 30ns + 60ns = 590ns.
So, rate of instruction execution = 100 instructions/590ns = 0.17 Giga instructions/sec.