mapping

Question

does direct mapping requires mux in its implementation?

Comments

in above question. latency was not negligible.

it is 0.6ns whereas for comparator it is 1.7ns. So why in direct mapping latency is calculated by only counting latency of comparator .

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lines(l) = 32 KB / 32 = 2 ^10

so the mux size should be 2^lines to 1 MUX

(i.e) 2^10 to 1 MUX

but in the question only 2 to 1 MUX is given

therefore its not this MUX that is mentioned, therefore since the latency of this mux is not menttioned

it is considered negligible

SET ASSOCIATIVE calculation requires OR gate  for the comparators

so the MUX mentioned in the question is for the OR gate

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ok...agreed.

but i have a doubt, here we need 17 no. of  2^10 to 1 MUX , so one 2^10 to 1 MUX can be implemented using  1023 no. of 2 to 1 MUX with total 10 no. of levels.

so by this calculation, 10*0.6ns =6ns is time taken by one 2^10 to 1 MUX,and since all 17 multiplexers are in parallel, all will execute in same time.

total time= 10*0.6ns + 1.7ns=7.7ns.

pls clear my doubt.