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Consider a 4 stage pipeline with stages named S1,S2,S3,S4. Let I1,I2,I3,I4 be 4 instructions and the number of clock-cycles needed by each instruction in each stage is given below.

The number of clock-cycles needed to complete the instruction cycle of the 4 instructions is ___.

asked in CO & Architecture by Loyal (3.3k points)   | 57 views
@arjun sir

thank u sir ... its very clear now ...
@vicky

There are stage buffers.  Yes it is assumed here  that a buffer between any 2 stage can hold more than 1 instruction's data at a time .

 "This is not a normal pipeline as stage delays are different. In a classic RISC pipeline we can just do with a single output buffer. But that will cause problem for this question. So, multiple buffers can be used here." as said by @Arjun

Bikram sir 

thanks ...now got it ...

When no 2 or more instructions use the same stage in a single cycle then why do we need to store multiple results at all. At any moment only one result is required in the buffer i.e the output of that particular stage with respect to the instructions.

Saswat Swarup  

Stage buffers are used in this question.

Here we assume that  a buffer between any 2 stage can hold more than 1 instruction's data at a time .

This is our assumption to match the answer :)

Because if we take single instruction's data in a buffer then no answer matches here . Hope you get my point !

 

1 Answer

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According to me Ur procedure is correct.

 

answered by Active (1.3k points)  
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how can you do s1 of 4 th instruction in 6 th clock-cycle ??? actually in the 6 th clock-cycle 3 rd instruction is in fetch -decode buffer .. if you do s1 of I4 in 6 th clock-cycle, then I3 will be over-written by I4 as a result we will lose I3 right ???


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