It requires (2n-1) half adders and (n-1) 2 input OR gates
for example: for 16 bit binary (parallel) adders we require 16 Full Adders to implement
that implies we need n Full adders,
else 1 Half Adder , 15 Full Adders -> 1 HA,(n-1) FA
else 31 HA, 0 FA -> (2n-1) HA
for first HA we don't require any OR gate and for the rest of the half adders we need (n-1) OR gates.
finally we need (2n-1) half adders and (n-1) OR gates