conflict misses

Question

A byte addressable computer has a small data cache capable of holding 16 32 bit words. Each cache block consists of four 32 bit words. For the following sequence of addresses (in hexadecimal). The miss ratio if 4-way set associative LRU cache  is used is ___________ ?

                100, 104, 108, 104, 107, 108, 105, 102, 108, 103.

Comments

As it will degenerates to associate it will not have conflict misses ..but miss ratio will remain 0.1..

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i didn't get you. how miss ratio will be 0?

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miss ratio will remain 0.1

Answer 1

Each cache is capable of holding 16 32 bit words. Here it’s a byte addressable so word is a byte. So, on the basis above

Cache size= 16 * (32/8) = 16 *4 = 64 byte.

block size=(4 *32)/8=16 bytes

Number of Blocks=cache size/block size=64/16=4 

number of sets=4 bytes/4way=1

as the number of sets are reduced to 1 then it will degenerates to associative mapping.

Tag	Offset	set bits
8 bits	3 bits	1

HEX	TAG	Block	Miss/Hit
100	0001-0000	0000	compulsory Miss
104	0001-0000	0100	compulsory miss
108	0001-0000	0000	compulsory miss
104	0010-0000	0100	Hit
107	0010-0000	0111	compulsory miss
108	0010-0000	0000	Hit
105	0010-0000	0101	compulsory miss
102	0010-0000	0010	compulsory miss
108	0010-0000	0000	Hit
103	0010-0000	0011	compulsory miss

As it will degenerates to associate it will not have conflict misses ..it will have compulsory miss=7

So miss ratio will be 7/10=0.70