1)
In Associative and Direct Mapping cache there is only 1 TAG stored in each cache line hence we don't need any MUX, while in Set Associative cache memories in every set there are more than one blocks stored and each has its own tag bits. If Cache memory is k-way associative so we need a MUX of size kx1 because when block tag matches with CPU provided tag that will be provided to fetch the required word.
2) only one MUX will be required of size kx1 when cache is k associative.
3) we compare tag bits with CPU provided Tag bits, hence we need a comparator of the size equal to the tag bits in all types of cache.
