For the circuit shown in the figure, the delay of the bubbled NAND gate is 2ns and that of the
counter is assumed to be zero.
If the clock (Clk) frequency is 1GHz, then the counter behaves as a:
(A) mod-5 counter
(B) mod-6 counter
(C) mod-7 counter
(D) mod-8 counter
What is approach applied for such type of question????