there are 5 stages, max stage delay is 900, suppose register delay is 10. cycle time will be 910 sec.
first instruction will take 5*910 seconds, and after that for each cycle ( for each 910 seconds) one instrcution will complete.
Suppose there are 1000 instructions, total time by a pipelined processor will be taken:
(K + n-1)*Tp = (5 + 999)*Tp = (1004)*Tp = !004*cycle Time now here you can see that 1004 cycles are needed to complete 1000 instructions. If n is very large value then k-1 can be ignored.
So CPI = 1