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what is the throughput  of pipelining ? If it has  4-stage pipelining with 800,500,400 and 300 picoseconds stage delays.
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1.25GIPS (giga instructions per second)??
please write all the steps and formula .

in pipelining CPI=1

clock rate= 800*10-12 s

1 instruction------>800*10-12 s

therefore throughput = # instructions per second = 1/(800*10-12) = 1.25GIPS

1. can u more focus on cpi=1 ??

2. I don't think throughput has any unit .

3.1 instruction------>800*10-12 s ? clarify it

What are you trying to do by entering such tags here?
sir i don't know how it is done .

I choose right tag and it automatically convert in this ...
oh. You are adding question on desktop? Which browser? Does this happen everytime?
sir first please comment on mine last comment on this question.

ya sir

ubuntu 16.04 firefox 64 bit

it happens most of time.

When pipeline becomes stable, for each cycle an new instruction will be processed. It means CPI=1

Cycle Time should be more or equal to the maximum stage delay so that each state gets enough time to be stable. here it is 800 pico seconds. By the way, register Delay is missing here so we can consider it negligible.

avg time for 1 instruction= 800x10^-12 secs

1 sec= 1/(800x10^-12)

=1.25 GIPS
@manu00x

let take a processor has 5 stages of stage delays : 300 sec , 500 sec , 600 sec , 400 sec ,900 sec

and it is stable

can u show how here cpi = 1 ?
@Hem
there are 5 stages, max stage delay is 900, suppose register delay is 10. cycle time will be 910 sec.
first instruction will take 5*910 seconds, and after that for each cycle ( for each 910 seconds) one instrcution will complete.
Suppose there are 1000 instructions, total time by a pipelined processor will be taken:
(K + n-1)*Tp = (5 + 999)*Tp = (1004)*Tp = !004*cycle Time now here you can see that 1004 cycles are needed to complete 1000 instructions. If n is very large value then k-1 can be ignored.
So CPI = 1
@manu00x , @bikram sir please see below

i think first instruction will take  : 300 + 500 + 600 +400+900 = 2700 sec

and further will take 900 sec for completion without any hazards .

(Above If I will consider register delay it will take )

2700+50 =2750 sec for first instruction

while for other it will be 910 sec in pipelining without any hazards consider.
@manu00x

Suppose there are 1000 instructions, total time by a pipelined processor will be taken:
(K + n-1)*Tp = (5 + 999)*Tp = (1004)*Tp = !004*cycle Time now here you can see that 1004 cycles are needed to complete 1000 instructions. If n is very large value then k-1 can be ignored.
So CPI = 1

buddy please elaborate last line :If n is very large value then k-1 can be ignored.
So CPI = 1. HOW?

Yes, we supposed to ignore k here as its small compared to n.

k = no of stages  , this can be ignored when n = number of tasks are large .

if we have a k-segment pipeline with a clock cycle time tp to execute n tasks.

The first task T1 requires a time equal to k*tp to complete its operation since there are k segments in pipeline. The remaining n-1 tasks emerge from the pipe at a rate of one task per clock cycle and they will be completed in k+n-1 clock cycles.

so when number of tasks is >> number of segments , that time k+n-1 = n clock cycles ..

so we supposed to ignore k here as its small compared to n .

When n is much more greater than k..then  k+n-1 is almost equal to n..that's why we can say CPI for pipeline is approx 1..